The present invention relates to acquisition of an input signal, and more particularly to a self-adjusting hold-off trigger for an acquisition system which is based on approximate time between trigger level crossings by the input signal.
U.S. Pat. No. 7,072,804, issued to Dennis J. Weller on Jul. 4, 2006, discloses a digital trigger circuit having an input filter for producing low and high frequency rejection trigger signals, as well as AC and DC trigger signals, derived from a digitized input signal. One of the four trigger signals is selected by a multiplexer and input to a trigger comparator having an upper trigger level and a lower trigger level to provide a desired amount of hysteresis, one trigger level being a desired trigger level and the other being a hysteresis level.
The hysteresis in the trigger comparator provides a noise rejection function. Low levels of noise are ignored. For rising edge trigger events, without hysteresis the noise may cause the falling edge of the digitized input signal to be detected as a rising edge. As shown in FIG. 1 a rising edge is detected on the transition from point A to point B. Without hysteresis other rising edges are detected on the transitions from point C to point D and again from point K to point L. A measurement instrument operator, attempting to trigger on rising edges, gets annoyed when the measurement instrument triggers on the transition from point K to point L, since this is clearly part of an overall falling edge. When the horizontal display scale is such that points J, K, L and M all occur within the same display column, the presence of a rising edge is not visible, and it appears that the acquisition system trigger circuit is malfunctioning. By adding hysteresis in the trigger comparator, as shown, the trigger circuit no longer triggers on the transition from point K to point L. A rising trigger edge only happens after the signal has passed below the hysteresis level and then passes above the desired trigger level.
Unfortunately a trigger comparator with hysteresis waits until the input trigger signal has passed above or below both levels (depending upon whether triggering is on the rising or falling edge of a signal) so that it doesn't mistakenly trigger on noise. When a state machine, which generates a trigger from the output of the trigger comparator, is set up for pulse width triggering, this may result in an error since the measured width from above the high level to below the low level may not accurately reflect the pulse width at the desired trigger level. Also rising edge trigger events stop occurring when the trigger level is near the minimum peak value for the digitized input signal, and falling edge trigger events stop occurring when the trigger level is near the maximum peak value for the digitized input signal.
U.S. Pat. No. 4,771,193, issued to Genichiro Ohta on Sep. 13, 1988 shows an analog circuit for triggering on a maximum length pulse within an input signal. As shown in FIG. 2 of the '193 patent, an input digital signal (a) produces a ramp signal (b) for each pulse, the height of the ramp being a function of the width of the pulse. A capacitor is charged, as shown by signal (c), and enables a sweep (I) that starts at the conclusion of the longest pulse. In this way the measuring instrument triggers on a non-signal interval indicated by the longest pulse width. This trigger circuit operates on a peak detection basis, i.e., triggering on the highest peak of the ramp signal (b).
U.S. Pat. No. 5,223,784, issued to Theodore G. Nelson, et al on Jun. 29, 1993, shows a circuit for triggering an acquisition system only once during a period of an input signal. A first trigger comparator detects qualifying trigger events in an input signal using a first reference trigger level, which qualifying trigger events charge a capacitor. A second trigger comparator compares the voltage on the capacitor with a second reference trigger level, and produces a pulse if the capacitor voltage has a predetermined relationship to the second reference trigger level. Subsequent trigger events which occur before a predetermined period of time, determined by an RC time constant, are unable to produce another trigger event.
The above-discussed patents are analog trigger circuit implementations. With the current digital storage oscilloscopes digital trigger circuit implementations are generally desired. Also these patents do not consider measuring an average duration between threshold crossings and then triggering only when a potential trigger event is preceded by a time related to the average duration.
What is desired is a self-adjusting hold-off trigger that uses an approximate time based upon average or peak time or duration between a qualified trigger event and a preceding edge event.